Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GQ100 /ETH /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOCLOCK)TSUCLKSEL 0TSUPRESC 0 (MIISEL)MIISEL 0 (GBLCLKEN)GBLCLKEN 0 (TXREFCLKSEL)TXREFCLKSEL

TSUCLKSEL=NOCLOCK

Description

Ethernet control register

Fields

TSUCLKSEL

TSU Clock selection value

0 (NOCLOCK): No TSU clock source selected

1 (PLL): Select system clock as TSU Clock

2 (RXCLK): Select ethernet RX Clock as TSU Clock

3 (REFCLK): Select ref clock as TSU Clock

4 (TSUEXTCLK): Select tsu external pin as TSU Clock

TSUPRESC

Clock division factor of TSUPRESC+1

MIISEL

MII select signal

GBLCLKEN

Global Clock Enable signal for Ethernet clocks tsu_clk, tx_clk, rx_clk and ref_clk

TXREFCLKSEL

REFCLK source select for RMII_TXD and RMII_TX_EN

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